1. Field of the Invention
The present invention relates to a semiconductor memory device and, more particularly, to a dynamic random access memory device having an internal power source which steps down or reduces the level of a power supply voltage applied to the memory from an outside (i.e., an external power supply voltage) and produces and supplies an internal power voltage to an internal circuit of the memory device as an operating power voltage.
2. Description of the Prior Art
It is well known in the art that latest dynamic memory devices constituted of MOS transistors employ a technique in which an internal power source circuit is used to reduce an external power supply voltage and supply an internal power voltage having a stepped-down voltage level to an internal memory circuit as an operating power voltage for the prevention of gate oxide film rupture and the occurrence of hot carriers and also for the reduction of power dissipation. Although this technique is very useful for fine pattern MOS transistors as well as in view of suppression of power consumption, the internal power voltage thus produced is required to be stabilized against the change in impedance of the internal memory circuit. For this purpose, the internal power source circuit utilizes a differential amplifier circuit which compares the internal power voltage with a reference voltage to stabilize the internal power voltage. That is, the internal power source performs a linear operation and thus consumes a d.c. power irrespective of access to the memory.
As is also well known in the art, the memory device has not only an active operation mode in which a data read and write access operations are performed, but also a standby mode waiting for the data read/write access. The power consumed by the memory device, in particular the power dissipation in the standby mode, is desirable to be as small as possible especially in a battery-operated apparatus or system.
However, the internal power source circuit always consumes power, as mentioned above. In the active operation mode, the power consumed by the internal power source circuit is very small as compared to that consumed by the internal memory circuit responsive to an access request. In the standby mode, on the other hand, a power consumed by the internal circuit becomes smaller, and hence the power consumed by the internal power source becomes a problem. The power consumed by the internal power source is, therefore, required to be cut down during standby mode.
For this purpose, such an internal power source circuit as shown in FIG. 6A has been proposed. This internal power source includes a first power supply circuit 1 and a second power supply circuit 2. The first power supply circuit 1 includes a differential amplifier circuit 11 operating on an external power voltage VCC. This amplifier 11 comprises a differential pair of N-channel MOS (called hereinafter "NMOS") transistors Q11 and Q12, an NMOS transistor Q13 as a constant current source, a pair of P-channel MOS (called hereinafter "PMOS") transistors Q14 and Q15 constituting a current mirror as a load, and a PMOS driver transistor 12 serving as an output buffer transistor to produce an internal power voltage VINT which is in turn supplied to the internal memory circuit (not shown). The transistor Q11 receives at its gate the internal power voltage VINT, and the transistor Q12 receives at its gate a reference voltage VREF. This reference voltage VREF is generated by a reference voltage generator (not shown) of a well-known band-gap regulator type and thus stabilized against the variation in external power voltage VCC as well as in an operating temperature. The reference voltage VREF is further supplied to the gate of the transistor Q13 to make it operate as a constant current source producing a current I1. Thus, the internal voltage VINT is controlled by the amplifier 11 to have the level equal to the reference voltage VREF by a negative feed loop.
The second power supply circuit 2 also includes a differential amplifier circuit 21. This circuit 21 comprises a differential pair of NMOS transistors Q21 and Q20 receiving the internal power voltage VINT and the reference voltage VREF, respectively, an NMOS transistor Q23 supplied at its gate with the reference voltage VREF and thus serving as a constant current source producing a constant current I2, a pair of PMOS transistors Q24 and Q25 operating as a current mirror circuit as a load, and a PMOS transistor 22 serving as an output buffer transistor coupled to the line to supply the internal power voltage VINT. Thus, the internal voltage VINT is further controlled to be equal to the reference voltage VREF.
Unlike the first internal power circuit 1, however, the second power circuit 2 further includes an NMOS transistor Q26 connected in series to the transistor Q23 and a PMOS transistor Q27 connected between the gate of the transistor 22 and the power line VCC. Still further, a control signal .phi.0 is supplied to the gates of the transistors Q26 and Q27. This control signal .phi.0 is derived by inverting a row address strobe signal RAS, as shown in FIG. 6B. This signal RAS is of a low active type. That is, address information supplied to a set of address input terminals (not shown) are fetched and latched as row address information in synchronism with the change of the row address strobe signal RAS from the high level to the low level, as well known in the art. The data read/write access operation is thereby initiated. On the other hand, the change of the signal RAS from the low level to the high level indicates the completion of the access operation and the standby mode. Accordingly, the transistors Q26 and Q27 are respectively turned ON and OFF during the time period in the active operation mode, and OFF and ON during the time period in the standby mode.
Thus, the first power circuit 1 is activated to operate not only in the active operation mode but also in the standby mode, whereas the second power circuit 2 is activated to operate only in the active operation mode and deactivated in the standby mode. In the standby mode, no access operation is performed and thus the internal memory circuit is in a steady state. That is, there is no substantial change in impedance of the internal memory circuit. Therefore, the first power supply 1 is sufficient to have small response speed and driving capability for stabilizing the internal power voltage VINT. The current I1 flowing through the transistor Q13, i.e., the operating current of the amplifier 11 is thus designed to be small to suppress the power dissipation consumed by the internal power source circuit in the standby mode. The constant current I1 is typically designed to be about 100 .mu.A.
On the other hand, in the active operation mode, the impedance of the internal memory circuit is considerably changed by the data read/write access. In order to stabilize the internal power voltage VINT against that impedance change, therefore, the internal power voltage VINT is required to be produced with large driving capability. To this end, the second power circuit 2 is also activated to control the internal power voltage VINT by the control signal .phi.0, as shown in FIG. 6(B). The high level control signal .phi.0 turns the transistor Q26 ON and the transistor Q27 OFF, as mentioned before. When the second power circuit 2 is activated, the driver transistor 22 is designed to have a large driving ability to stabilize the internal power voltage VINT, and it is generally ten times in the driving ability as large as the driver transistor 12 of the first circuit 1. Moreover, the amplifier circuit 21 is also designed to have a high response speed by being supplied with the large constant current I2 through the transistors Q23 and Q26. The constant current I2 is designed to be typically about 1 to 2 mA.
Thus, the dissipation current becomes I1+I2 during the time in the active operation mode and I1 during the time in the standby mode, as shown in FIG. 6(B), so that a wasteful current does not flow during the standby mode. The reduction of the power consumption of the internal power source is thereby achieved.
However, further reduction in power consumption is a big concern in current memory devices. Such a memory device requires as much power consumption reduction as possible.